1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more particularly, to a method of forming a data storage capacitor with a wide electrode area, and thus a high capacitance, for a DRAM (dynamic random access memory) device.
2. Description of Related Art
The DRAM is a volatile semiconductor read/write memory which is widely used in computers as the primary random access data storage means. FIG. 1 is a schematic diagram showing the equivalent circuit of each memory cell of a typical DRAM device, which includes a transfer transistor T and a data storage capacitor C. The transfer transistor T has a gate connected to a word line WL, a source connected to a bit line BL, and a drain connected to one electrode 6 of the data storage capacitor C. The opposed electrode 8 of the data storage capacitor C is connected to a fixed voltage source. Between the two electrodes 6, 8 is there formed with a dielectric layer 7. Whether this memory cell stores a binary data bit 0 or 1 is dependent on whether the data storage capacitor C is charged or not. In the fabrication of the DRAM device, it is desired that the capacitance of the data storage capacitor C be made as large as possible for high retaining capability and reliability of the data stored thereon.
In conventional DRAMs having a storage capacity less than 1 MB (megabit), it is a customary practice to form a two-dimensional capacitive structure, called a planar-type capacitor, as the data storage capacitor. FIG. 2 is a schematic sectional diagram showing the semiconductor structure of a conventional planar-type capacitor in a DRAM device. As shown, the DRAM device includes a semiconductor substrate 10 on which a field oxide layer 11 is formed to set apart each active region where one memory cell of the DRAM device is formed. A transfer transistor T, which includes a gate oxide layer 12, a gate 13, and a pair of source/drain regions 14, is formed on the substrate 10. Moreover, a dielectric layer 7 and a conductive layer 8 are formed beside the transfer transistor T; wherein the portions of the dielectric layer 7 and conductive layer 8 that are laid in the active region (as designated by the reference numeral 6) are used to serve as the data storage capacitor C of the transfer transistor T. It can be clearly seen from FIG. 2 that the planar-type capacitor should take up quite a large area on the substrate 10 in order to provide a large enough capacitance to allow reliable data retaining capability for the capacitor. The planar-type capacitor is therefore not suitable for use in high-integration DRAM devices where circuit layout space is limited.
In higher capacity DRAMs, such as 4 MB or higher DRAMs, a three-dimensional capacitive structure, such as a stacked-type or a trench-type capacitor, is used instead as the data storage capacitor.
FIG. 3 is a schematic sectional diagram showing the semiconductor structure of a conventional stack-type capacitor for use in a 4 MB DRAM device. As shown, the DRAM device includes a semiconductor substrate 10 on which a field oxide layer 11, a gate oxide layer 12, a gate 13, and a pair of source/drain regions 14 are formed, which in combination constitute a transfer transistor T. Further, an insulating layer 15 is formed over the wafer, which is selectively removed to form a contact opening to expose one of the source/drain regions 14. In the contact opening, a first conductive layer 6 (such as a polysilicon layer), a dielectric layer 7, and a second conductive layer 8 are successively formed, which in combination constitute a data storage capacitor for the DRAM device. The first conductive layer 6 serves as one electrode and the second conductive layer 8 serves as the opposing electrode. The stacked-type capacitor allows a high capacitance for reliable data retaining even when the DRAM device is further downsized. However, for still higher levels of integration, such as the 64 MB or higher DRAMs, the stacked-type capacitors can no longer meet the requirements.
FIG. 4 is a schematic sectional diagram showing the semiconductor structure of a conventional trench-type capacitor for use in a DRAM device. As shown, the DRAM device includes a semiconductor substrate 10 on which a field oxide layer 11, a gate oxide layer 12, a gate 13, and a pair of source/drain regions 14 are formed, which in combination constitute a transfer transistor T. Further, a trench is formed near one of the source/drain regions 14 that serves as drain; then, in the trench a capacitive structure is formed to serve as the data storage capacitor C, which includes a base electrode 6 (which is part of the substrate 10), a dielectric layer 7, and a polysilicon-based opposing electrode 8. This trench-type capacitor has a high capacitance due to its extended electrode surface in the trench. However, one drawback to this trench-type capacitor is that the forming of the trench by etching would easily cause crystalline defects to the substrate 10, which would then cause leakage current in the resultant DRAM device. Moreover, the etching rate decreases as the aspect ratio of the trench is increased, which would cause the fabrication process difficult to perform, thus affecting the throughput of the manufacture of the DRAM device.
Further, in the fabrication of a so-called capacitor-over-bitline (COB) structure with the submicron 0.25-.mu.m design rule, the contact windows are formed in very close proximity to the nearby gates and polysilicon-based bit lines. In the subsequent etching process through these contact windows, the gates and the bit lines could therefore be damaged by the etching. Conventionally, there are two solutions to this problem: one solution is to use the self-aligned contact (SAC) technique to form silicon nitride based sidewall spacers both on the gate electrodes and the polysilicon-based bit lines so as to protect them from the etching; and the other solution is to use the phase-shift mask (PSM) technique. These two techniques, however, are still immature and thus can be difficult and troublesome to use.